LAN9311 datasheet(97/459 Pages) SMSC

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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9311/LAN9311i

Revision 1.6 (08-18-09)

DATASHEET

The emulated auto-negotiation process is much simpler than the real process and can be categorized

into three steps:

1. Bit 5 (Auto-Negotiation Complete) is set in the Virtual PHY Basic Status Register

(VPHY_BASIC_STATUS).

2. Bit 1 (Page Received) is set in the Virtual PHY Auto-Negotiation Expansion Register

(VPHY_AN_EXP).

3. The auto-negotiation result (speed and duplex) is determined and registered.

The auto-negotiation result (speed and duplex) is determined using the Highest Common Denominator

(HCD) of the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) and Virtual PHY

Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) as

specified in the IEEE 802.3 standard. The technology ability bits of these registers are ANDed, and if

there are multiple bits in common, the priority is determined as follows:

100Mbps Full Duplex (highest priority)

100Mbps Half Duplex

10Mbps Full Duplex

10Mbps Half Duplex (lowest priority)

For example, if the full capabilities of the Virtual PHY are advertised (100Mbps, Full Duplex), and if

the link partner is capable of 10Mbps and 100Mbps, then auto-negotiation selects 100Mbps as the

highest performance mode. If the link partner is capable of half and full-duplex modes, then auto-

negotiation selects full-duplex as the highest performance operation. In the event that there are no bits

in common, an emulated Parallel Detection is used.

The Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) defaults to having all four

ability bits set. These values can be reconfigured via software. Once the auto-negotiation is complete,

any change to the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) will not take

affect until the auto-negotiation process is re-run. The emulated link partner always advertises all four

abilities (100BASE-X full duplex, 100BASE-X half duplex, 10BASE-T full duplex, and 10BASE-T half

duplex) in the Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register

(VPHY_AN_LP_BASE_ABILITY). Neither the Virtual PHY or the emulated link partner support next

page capability, remote faults, or 100BASE-T4.

If there is at least one common selection between the emulated link partner and the Virtual PHY

advertised abilities, then the auto-negotiation succeeds, the Link Partner Auto-Negotiation Able bit 0

of the Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) is set, and the technology

ability bits in the Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register

(VPHY_AN_LP_BASE_ABILITY) are set to indicate the emulated link partners abilities.

Note:

For the Virtual PHY, the auto-negotiation register bits (and management of such) are used by

the Host MAC. So the perception of local and link partner is reversed. The local device is the

Host MAC, while the link partner is the switch fabric. This is consistent with the intention of the

Virtual PHY.

7.3.1.1

Parallel Detection

In the event that there are no common bits between the advertised ability and the emulated link

partners ability, auto-negotiation fails and emulated parallel detect is used. In this case, the Link

Partner Auto-Negotiation Able (bit 0) in the Virtual PHY Auto-Negotiation Expansion Register

(VPHY_AN_EXP) will be cleared, and the communication set to 100Mbps half-duplex. Only one of the

technology ability bits in the Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register

(VPHY_AN_LP_BASE_ABILITY) will be set, indicating the emulated parallel detect result.

7.3.1.2

Disabling Auto-Negotiation

Auto-negotiation can be disabled in the Virtual PHY by clearing bit 12 (VPHY_AN) of the Virtual PHY

Basic Control Register (VPHY_BASIC_CTRL). The Virtual PHY will then force its speed of operation

to reflect the speed (bit 13) and duplex (bit 8) of the Virtual PHY Basic Control Register

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