ADE7878 datasheet(36/92 Pages) AD

36 / 92 page

ADE7878

Rev. 0 | Page 36 of 92

advance in the voltage channel signal path from +61.5 μs to

−374.0 μs, respectively. Negative values written to the PHCAL

registers represent a time advance whereas positive values

represent a time delay. One LSB is equivalent to 0.976 μs of time

delay or time advance (clock rate of 1.024 MHz). With a line

frequency of 60 Hz, this gives a phase resolution of 0.0211°

(360° × 60 Hz/1.024 MHz) at the fundamental. This corresponds

to a total correction range of −8.079° to +1.329° at 60 Hz. At

50 Hz, the correction range is −6.732° to +1.107° and the

resolution is 0.0176° (360° × 50 Hz/1.024 MHz).

Given a phase error of x degrees measured using the phase

voltage as the reference, the corresponding LSBs are computed

dividing x by the phase resolution (0.0211°/LSB for 60 Hz and

0.0176°/LSB for 50 Hz). Results between −383 and +63 only are

acceptable; numbers outside this range are not acceptable. If the

result is negative, the absolute value is written into the PHCAL

registers. If the result is positive, 512 is added to the result

before writing it into xPHCAL.

APHCAL,

BPHCAL, or

CPHCAL =

⎪

⎭

⎪

⎬

⎫

⎪

⎩

⎪

⎨

⎧

≤

512

resolution

phase

resolution

phase

(8)

Figure 52 illustrates how the phase compensation is used to remove

x = −1° phase lead in IA of the current channel from the

external current transducer (equivalent of 55.5 μs for 50 Hz

systems). To cancel the lead (1°) in the current channel of

Phase A, a phase lead must be introduced into the corres-

ponding voltage channel. Using Equation 8, APHCAL is 57,

rounded up from 56.8. The phase lead is achieved by

introducing a time delay of 55.73 μs into the Phase A current.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words. As shown in Figure 51, the APHCAL,

BPHCAL, and CPHCAL 10-bit registers are accessed as 16-bit

registers with the six MSBs padded with 0s.

0000 00

10 9

xPHCAL

Figure 51. xPHCAL Registers Communicated As 16-Bit Registers

PHASE

CALIBRATION

APHCAL = 57

ADC

PGA3

VAP

ADC

PGA1

IAP

IAN

PHASE COMPENSATION

ACHIEVED DELAYING

IA BY 56µs

50Hz

1°

Figure 52. Phase Calibration on Voltage Channels

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