ADE7878 datasheet(82/92 Pages) AD

82 / 92 page

ADE7878

Rev. 0| Page 82 of 92

Bit Location

Bit Name

Default Value

Description

VSPHASE[0]

When this bit is set to 1, the Phase A voltage generated Bit 16 (SAG) in the

STATUS1[31:0] register.

VSPHASE[1]

When this bit is set to 1, the Phase B voltage generated Bit 16 (SAG) in the

STATUS1[31:0] register.

VSPHASE[2]

When this bit is set to 1, the Phase C voltage generated Bit16 (SAG) in the STATUS1[31:0]

Reserved

Reserved. This bit is always 0.

Table 36. PHNOLOAD Register (Address 0xE608)

Bit

Location

Bit Name

Default Value

Description

NLPHASE[0]

0: Phase A is out of no load condition based on total active/reactive powers.

1: Phase A is in no load condition based on total active/reactive powers. This bit is set

together with Bit 0 (NLOAD) in the STATUS1[31:0] register.

NLPHASE[1]

0: Phase B is out of no load condition based on total active/reactive powers.

1: Phase B is in no load condition based on total active/reactive powers. This bit is set

together with Bit 0 (NLOAD) in the STATUS1[31:0] register.

NLPHASE[2]

0: Phase C is out of no load condition based on total active/reactive powers.

1: Phase C is in no load condition based on total active/reactive powers. This bit is set

together with Bit 0 (NLOAD) in the STATUS1[31:0] register.

FNLPHASE[0]

0: Phase A is out of no load condition based on fundamental active/reactive powers.

1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is

set together with Bit 1 (FNLOAD) in STATUS1[31:0].

FNLPHASE[1]

0: Phase B is out of no load condition based on fundamental active/reactive powers.

1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is

set together with Bit 1 (FNLOAD) in STATUS1[31:0].

FNLPHASE[2]

0: Phase C is out of no load condition based on fundamental active/reactive powers.

1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is

set together with Bit 1 (FNLOAD) in STATUS1[31:0].

VANLPHASE[0]

0: Phase A is out of no load condition based on apparent power.

1: Phase A is in no load condition based on apparent power. This bit is set together with Bit 2

(VANLOAD) in the STATUS1[31:0] register.

VANLPHASE[1]

0: Phase B is out of no load condition based on apparent power.

1: Phase B is in no load condition based on apparent power. This bit is set together with Bit 2

(VANLOAD) in the STATUS1[31:0] register.

VANLPHASE[2]

0: Phase C is out of no load condition based on apparent power.

1: Phase C is in no load condition based on apparent power. This bit is set together with Bit 2

(VANLOAD) in the STATUS1[31:0] register.

15:9

Reserved

000 0000

Reserved. These bits are always 0.

Table 37. COMPMODE Register (Address 0xE60E)

Bit

Location

Bit Name

Default

Value

Description

TERMSEL1[0]

Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1 output.

Phase A is included in the CF1 outputs calculations.

TERMSEL1[1]

Phase B is included in the CF1 outputs calculations.

TERMSEL1[2]

Phase C is included in the CF1 outputs calculations.

TERMSEL2[0]

Setting all TERMSEL2[2:0] to 1 signifies the sum of all three phases is included in the CF2 output.

Phase A is included in the CF2 outputs calculations.

TERMSEL2[1]

Phase B is included in the CF2 outputs calculations.

TERMSEL2[2]

Phase C is included in the CF2 outputs calculations.

TERMSEL3[0]

Setting all TERMSEL3[2:0] to 1 signifies the sum of all three phases is included in the CF3 output.

Phase A is included in the CF3 outputs calculations.

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