ADE7878 datasheet(61/92 Pages) AD

61 / 92 page

ADE7878

Rev. 0 | Page 61 of 92

All the other gi coefficients are equal to 0.

software reset, the CRC is computed on the default values of

the registers, giving the result of 0x33666787.

FB(j) = aj – 1 XOR b31(j – 1)

(51)

Figure 77 shows how the LFSR works. Bits[a0, a1,…, a255]

represent the bits from the list of registers presented previously

in this section. Bit a0 is the least significant bit of the first

internal register to enter LFSR; Bit a255 is the most significant bit

of the MASK0[31:0] register, the last register to enter LFSR. The

formulas that govern LFSR are as follows:

b0(j) = FB(j) AND g0

(52)

bi(j) = FB(j) AND gi XOR bi − 1(j – 1), i = 1, 2, 3, ..., 31

(53)

Equation 51, Equation 52, and Equation 53 must be repeated for

j = 1, 2, …, 256. The value written into the CHECKSUM[31:0]

CRC after the bits from the reserved internal register have passed

through LFSR is 0x2D32A389. It is obtained at Step j = 48.

bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that form

the CRC. Bit b0 is the least significant bit, and Bit b31 is the most

significant.

Two different approaches can be followed in using the

CHECKSUM register. One is to compute the CRC based on

the relations (47) to (51) and then compare the value against the

CHECKSUM register. Another is to periodically read the

CHECKSUM[31:0] register. If two consecutive readings differ,

it can be assumed that one of the registers has changed value

and, therefore, that the ADE7878 has changed configuration.

The recommended response is to initiate a hardware/software

reset that sets the values of all registers to the default, including

the reserved ones, and then reinitialize the configuration

registers.

gi, i = 0, 1, 2, …, 31 are the coefficients of the generating

polynomial defined by the IEEE802.3 standard as follows:

G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5

+ x4 + x2 + x + 1

(49)

g0 = g1 = g2 = g4 = g5 = g7 = 1

g8 = g10 = g11 = g12 = g16 = g22 = g26 = 1

(50)

0 15

255 248

240

232

224

216

70 7

0 7

8 7

MASK0 MASK1 COMPMODE

CFMODE

GAIN

INTERNAL

LFSR

GENERATOR

Figure 76. CHECKSUM[31:0] Register Calculation

LFSR

g31

b31

a255, a254,....,a2, a1, a0

Figure 77. LFSR Generator Used in CHECKSUM[31:0] Register Calculation

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