ADS58C48IPFPR datasheet(40/70 Pages) TI

40 / 70 page

1.65

1.7

1.75

1.8

1.85

1.9

1.95

83.2

83.4

83.6

83.8

84.2

84.4

84.6

84.8

66.2

66.25

66.3

66.35

66.4

66.45

66.5

66.55

66.6

66.65

66.7

SFDR

DRVDD SUPPLY (V)

SNR

Fin = 40MHz

0.1

0.4

0.7

1.3

1.6

1.9

2.2

Fin = 40MHz

Fin =150MHz

Differential Clock Amplitude (Vpp)

65.7

65.8

65.9

66.1

66.2

66.3

66.4

66.5

66.6

66.7

66.8

66.9

0.1

0.4

0.7

1.3

1.6

1.9

2.2

Fin = 40MHz

Fin =150MHz

Differential Clock Amplitude (Vpp)

ADS58C48

SLAS689 – MAY 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP

differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High Perf Mode disabled, 0 dB gain,

DDR LVDS output interface, 32k point FFT (unless otherwise noted)

PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE (CMOS)

Figure 37.

SFDR

SNR

INPUT CLOCK AMPLITUDE

Figure 38.

Figure 39.

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