ADS58C48IPFPR datasheet(9/70 Pages) TI

9 / 70 page

ADS58C48

www.ti.com

SLAS689 – MAY 2010

TIMING CHARACTERISTICS – LVDS AND CMOS MODES

(1) (continued)

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock, CLOAD =

5 pF

(2), R

LOAD = 100 Ω

(3), unless otherwise noted.

MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, DRVDD = 1.7 V to

1.9 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tCLKRISE,

Output clock rise time

Rise time measured from 20% to 80% of DRVDD

0.6

tCLKFALL

Output clock fall time

Fall time measured from 80% to 20% of DRVDD

1 ≤ Sampling frequency ≤ 150 MSPS

Table 2. LVDS Timings Across Sampling Frequencies

SETUP TIME, ns

HOLD TIME, ns

SAMPLING FREQUENCY, MSPS

MIN

TYP

MAX

MIN

TYP

MAX

185

0.7

1.30

0.35

0.70

170

0.9

1.55

0.35

0.70

150

1.2

1.9

0.35

0.70

125

1.9

2.6

0.35

0.70

Table 3. CMOS Timings Across Sampling Frequencies

TIMINGS SPECIFIED WITH RESPECT TO INPUT CLOCK

SAMPLING FREQUENCY

tSTART, ns

DATA VALID TIME, ns

MSPS

MIN

TYP

MAX

MIN

TYP

MAX

185

–1.4

3.6

4.2

170

–2.8

4.2

4.7

150

–4.6

4.8

5.4

125

1.0

6.2

6.8

TIMINGS SPECIFIED WITH RESPECT TO CLKOUT

SAMPLING FREQUENCY

tPDI, CLOCK PROPAGATION

SETUP TIME, ns

HOLD TIME, ns

MSPS

DELAY, ns(1)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

150

2.0

2.8

2.0

2.8

125

2.6

3.5

2.6

3.5

4.8

5.8

4.8

5.8

80 to 150

6.5

(1)

At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.

Submit Documentation Feedback

Product Folder Link(s) :ADS58C48

ADS58C48IPFPR Scheda tecnica(PDF) 9 Page - Texas Instruments

ADS58C48IPFPR Scheda tecnica(HTML) 9 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Scheda tecnica Scarica

Link URL