FS401LF datasheet(88/104 Pages) ETC2

88 / 104 page

FS401, FS403

PRODUCT SPECIFICATION

REV. NO. 1.7

JANUARY 24, 2007

SIOA10/7

SIOA0

Address

224

276

Table 5. Serial Port Addresses

5.4.1 Data Transfer via Serial Interface

If a slave device, such as the FS400 does not acknowledge the master device during a write sequence,

SIODATA remains HIGH so the master can generate a stop signal. If the master device does not

acknowledge the FS400 during a read sequence, the FS400 interprets this as “end of data”. SIODATA

remains HIGH so the master can generate a stop signal.

To write data to a specific FS400 control register, the 8-bit pointer must be loaded with the address of the

target control register after the slave address has been established. Value of the pointer is the base

address for subsequent write operations. The pointer address auto-increments by after each control

not increment and remain at its maximum value of 6 and send an acknowledge signal, ACK.

Data is read from the control registers of the FS400 in a similar manner, except that two data transfer

operations are required:

Write the slave address byte with bit R/W = L.

Write the pointer byte.

Write the slave address byte with bit R/W = H

Read the control register indexed by the pointer.

Preceding each slave write, there must be a start cycle. Following the pointer byte there should be a stop

cycle. Sequential registers may be accessed by repeated read cycles since pointer auto-increments after

each byte transfer. After the last read, there must be a stop cycle comprising a LOW-to-HIGH transition

of SIODATA while SIOCLK is HIGH. (see Figure 16, right waveform)

A repeated start signal occurs when the master device driving the serial interface generates a start signal

without first generating a stop signal to terminate the current communication. This is used to change the

mode of communication (read, write) between the slave and master without releasing the serial interface

lines.

5.4.2 Serial Interface Read/Write Examples

Examples below show how serial bus cycles can be linked together for single and multiple register read

and write access cycles. For sequential register accesses, each ACK handshake initiates further

SIOCLK clock cycles from the master to transfer the next data byte.

5.4.2.1 Write to one control register

• Start signal

• Slave Address byte (R/W bit = LOW)

• Pointer Address byte

• Data byte to register

• Stop signal

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