PIC16F720-ESLASHML datasheet(32/244 Pages) MICROCHIP

32 / 244 page

PIC16F/LF720/721

DS41430A-page 32

 2010 Microchip Technology Inc.

3.6

Time-out Sequence

On power-up, the time-out sequence is as follows: first,

PWRT time-out is invoked after POR has expired, then

OST is activated after the PWRT time-out has expired.

The total time-out will vary based on oscillator configu-

ration and PWRTE bit status. For example, in EC mode

with PWRTE bit = 1 (PWRT disabled), there will be no

time-out at all. Figure 3-4, Figure 3-5 and Figure 3-6

depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 3-5). This is useful for testing purposes or

to synchronize more than one PIC16F/LF720/721

device operating in parallel.

Table 3-5 shows the Reset conditions for some special

registers.

3.7

Power Control (PCON) Register

The Power Control (PCON) register has two Status bits

to indicate what type of Reset that last occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable

the

brown-out

circuit

disabled

(BOREN<1:0> = 00 in the Configuration Word register).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

For more information, see Section 3.5 “Brown-Out

Reset (BOR)”.

FIGURE 3-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

TABLE 3-4:

TIME-OUT IN VARIOUS SITUATIONS

Oscillator Configuration

Power-up

Brown-out Reset

Wake-up from

Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

EC, INTOSC

TPWRT

—TPWRT

——

TABLE 3-5:

RESET BITS AND THEIR SIGNIFICANCE

POR

BOR

Condition

0u11

Power-on Reset

1011

Brown-out Reset

uu0u

WDT Reset

uu00

WDT Wake-up

uuuu

MCLR Reset during normal operation

uu10

MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

Internal Reset

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