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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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MB90F482BPMC Scheda tecnica(PDF) 97 Page - fujitsu semiconductor |
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MB90F482BPMC Scheda tecnica(HTML) 97 Page - fujitsu semiconductor |
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97 / 124 page  MB90480B/485B Series DS07-13722-11E 97 (6) Bus Write Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. Parameter Sym- bol Pin name Condi- tion Value Unit Remarks Min Max Valid address → WR↓ time tAVWL Address, WR ⎯ tCP* − 15 ⎯ ns WR pulse width tWLWH WRL, WRH ⎯ 3 tCP* / 2 − 25 ⎯ ns 16 MHz < fCP ≤ 25 MHz ⎯ 3 tCP* / 2 − 20 ⎯ ns 8 MHz < fCP ≤ 16 MHz Valid data output → WR↑ time tDVWH Data, WR ⎯ 3 tCP* / 2 − 15 ⎯ ns WR ↑ → data hold time tWHDX WR, Data ⎯ 10 ⎯ ns 16 MHz < fCP ≤ 25 MHz ⎯ 20 ⎯ ns 8 MHz < fCP ≤ 16 MHz ⎯ 30 ⎯ ns fCP ≤ 8 MHz WR ↑ → address valid time tWHAX WR, Address ⎯ tCP* / 2 − 10 ⎯ ns WR ↑ → ALE↑ time tWHLH WR, ALE ⎯ tCP* / 2 − 15 ⎯ ns WR ↓ → CLK↑ time tWLCH WR, CLK ⎯ tCP* / 2 − 17 ⎯ ns |
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