M48Z129Y, M48Z129V

Operation modes

Doc ID 5716 Rev 7

7/20

2

Operation modes

The M48Z129Y/V also has its own power-fail detect circuit. This control circuitry constantly

the circuit write protects the SRAM, providing data security in the midst of unpredictable

maintaining data until valid power is restored.

Table 2.

Operating modes

Note:

2.1

READ mode

The M48Z129Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip

enable) is low. The unique address specified by the 17 address inputs defines which one of

the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins

E and G access times are also satisfied. If the E and G access times are not met, valid data

The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are

the address inputs are changed while E and G remain active, output data will remain valid

Figure 4.

Address controlled, READ mode AC waveforms

Note:

Chip enable (E) and output enable (G) = low, WRITE enable (W) = high

Mode

E

G

W

DQ0-DQ7

Power

Deselect

4.5 to 5.5 V

or

3.0 to 3.6 V

X

X

High Z

Standby

WRITE

Active

READ

Active

READ

High Z

Active

Deselect

(1)

1.

See Table 10 for details.

X

X

X

High Z

CMOS standby

Deselect

≤ VSO(1)

X

X

X

High Z

Battery backup mode

AI02324

tAVAV

tAVQV

tAXQX

DATA VALID

A0-A16

DQ0-DQ7

VALID

DATA VALID