M48Z129V datasheet(10/20 Pages) STMICROELECTRONICS

10 / 20 page

Operation modes

M48Z129Y, M48Z129V

10/20

Doc ID 5716 Rev 7

Table 4.

WRITE mode AC characteristics

2.3

Data retention mode

With valid VCC applied, the M48Z129Y/V operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting

itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high

impedance and all inputs are treated as “Don’t care”.

Note:

A power failure during a WRITE cycle may corrupt data at the current addressed location,

but does not jeopardize the rest of the RAM’s content. At voltages below VPFD(min), the

memory will be in a write protected state, provided the VCC fall time is not less than tF. The

M48Z129Y/V may respond to transient noise spikes on VCC that cross into the deselect

window during the time the device is sampling VCC. Therefore, decoupling of the power

supply lines is recommended.

When VCC drops below VSO, the control circuit switches power to the internal battery,

preserving data. The internal energy source will maintain data in the M48Z129Y/V for an

accumulated period of at least 10 years at room temperature. As system power rises above

VSO, the battery is disconnected, and the power supply is switched to external VCC.

Deselect continues for tREC after VCC reaches VPFD(max).

For more information on battery storage life refer to the application note AN1012.

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).

M48Z129Y

M48Z129V

Unit

–70

–85

Min

Max

Min

Max

tAVAV

WRITE cycle time

tAVWL

Address valid to WRITE enable low

tAVEL

Address valid to chip enable low

tWLWH

WRITE enable pulse width

tELEH

Chip enable low to chip enable high

tWHAX

WRITE enable high to address transition

tEHAX

Chip enable high to address transition

tDVWH

Input valid to WRITE enable high

tDVEH

Input valid to chip enable high

tWHDX

WRITE enable high to input transition

tEHDX

Chip enable high to input transition

tWLQZ

(2)(3)

CL = 5 pF (see Figure 9).

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable low to output Hi-Z

tAVWH

Address valid to WRITE enable high

tAVEH

Address valid to chip enable high

tWHQX

(2)(3)

WRITE enable high to output transition

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