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M48Z129V Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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M48Z129V Scheda tecnica(HTML) 1 Page - STMicroelectronics |
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1 / 20 page ![]() June 2010 Doc ID 5716 Rev 7 1/20 1 M48Z129Y M48Z129V 5.0 V or 3.3 V, 1 Mbit (128 Kb x 8) ZEROPOWER® SRAM Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of power ■ Microprocessor power-on reset (reset valid even during battery backup mode) ■ Battery low pin - provides warning of battery end-of-life ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages (VPFD = power-fail deselect voltage): –M48Z129Y: VCC = 4.5 to 5.5 V 4.2 V ≤ VPFD ≤ 4.5 V (contact the ST sales office for availability) –M48Z129V: VCC = 3.0 to 3.6 V 2.7 V ≤ VPFD ≤ 3.0 V ■ Self-contained battery in the CAPHAT™ DIP package ■ Pin and function compatible with JEDEC standard 128 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect 32 1 PMDIP32 module (PM) www.st.com |
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