EN25Q64-104FIP datasheet(30/60 Pages) EON

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EN25Q64

Rev. J, Issue Date: 2011/07/07

Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in

random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-

bit address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4

dummy clocks -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low

(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown

in Figure 16.

In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,

F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)

instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And

afterwards CS# is raised, the system then will escape from performance enhance mode and return to

normal operation.

While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)

instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.

The instruction sequence is shown in Figure 16.1 while using the Enable Quad Peripheral Interface mode

(EQPI) (38h) command.

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