EN25Q64-104FIP datasheet(39/60 Pages) EON

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This Data Sheet may be revised by subsequent versions

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or modifications due to changes in technical specifications.

EN25Q64

Rev. J, Issue Date: 2011/07/07

Figure 21. Deep Power-down Instruction Sequence Diagram

Release from Deep Power-down and Read Device ID (RDI)

Once the device has entered the Deep Power-down mode, all instructions are ignored except the

Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes

the device out of the Deep Power-down mode.

Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature

that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for

reasons of backward compatibility, only, and should not be used for new designs. New designs should,

instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.

When used only to release the device from the power-down state, the instruction is issued by driving

the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 22. After

the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other

instructions will be accepted. The CS# pin must remain high during the tRES1 time duration.

When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by

driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device

ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in

Figure 23. The Device ID value for the EN25Q64 are listed in Table 5. The Device ID can be read

continuously. The instruction is completed by driving CS# high.

When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device

was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is

immediate. If the device was previously in the Deep Power-down mode, though, the transition to the

Standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2

(max), as specified in Table 11. Once in the Stand-by Power mode, the device waits to be selected, so

that it can receive, decode and execute instructions.

Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep

Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the

device, and can be applied even if the Deep Power-down mode has not been entered.

Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or

Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in

progress.

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