EN25Q64-104FIP datasheet(35/60 Pages) EON

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or modifications due to changes in technical specifications.

EN25Q64

Rev. J, Issue Date: 2011/07/07

Figure 18. Sector Erase Instruction Sequence Diagram

Block Erase (BE) (D8h)

The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be

accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write

Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-

struction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see

Table 2) is a valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low

for the entire duration of the sequence.

The instruction sequence is shown in Figure 19. Chip Select (CS#) must be driven High after the eighth

bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not

executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose du-

ration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-

timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset.

A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2,

BP1, BP0) bits (see Table 3) is not executed.

The instruction sequence is shown in Figure 19.1 while using the Enable Quad Peripheral Interface mode

(EQPI) (38h) command.

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