SN8A1702AX datasheet(82/112 Pages) SONIX

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Preliminary

SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 82

Revision 0.5

INT0 (P0.0) INTERRUPT OPERATION

The P0.0 interrupt trigger direction is control by PEDGE register.

PEDGE initial value = 0xx0 0xxx

0BFH

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PEDGE

PEDGEN

P00G1

P00G0

R/W

Bit7

PEDGEN: Interrupt and wakeup trigger edge control bit.

0 = Disable edge trigger function.

Port 0: Low-level wakeup trigger and falling edge interrupt trigger.

Port 1: Low-level wakeup trigger.

1 = Enable edge trigger function.

P0.0:

Wakeup and interrupt trigger is controlled by P00G1 and P00G0 bits.

Port 1: Level change (falling or rising edge) wakeup trigger.

Bit[4:3]

P00G[1:0]: Port 0.0 edge select bits.

00 = reserved,

01 = rising edge,

10 = falling edge,

11 = rising/falling bi-direction.

Example: INT0 interrupt request setup.

B0BSET

FP00IEN

; Enable INT0 interrupt service

B0BCLR

FP00IRQ

; Clear INT0 interrupt request flag

B0BSET

FGIE

; Enable GIE

Example: INT0 interrupt service routine.

ORG

; Interrupt vector

JMP

INT_SERVICE

INT_SERVICE:

B0XCH

A, ACCBUF

; Store ACC value.

B0MOV

A, PFLAG

B0MOV

PFLAGBUF, A

B0BTS1

FP00IRQ

; Check P00IRQ

JMP

EXIT_INT

; P00IRQ = 0, exit interrupt vector

B0BCLR

FP00IRQ

; Reset P00IRQ

; INT0 interrupt service routine

EXIT_INT:

B0MOV

A, PFLAGBUF

B0MOV

PFLAG, A

B0XCH

A, ACCBUF

; Restore ACC value.

RETI

; Exit interrupt vector

When the INT0 trigger occurs, the P00IRQ will be set to “1” no matter the P00IEN is enable or disable. If the P00IEN =

1 and the trigger event P00IRQ is also set to be “1”.

As the result, the system will execute the interrupt vector (ORG

8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be “1”. Moreover, the system won’t execute interrupt

vector even when the P00IRQ is set to be “1”.

Users need to be cautious with the operation under multi-interrupt

situation.

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