SN8A1702AX datasheet(43/112 Pages) SONIX

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Preliminary

SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 43

Revision 0.5

OSCM REGISTER DESCRIPTION

The OSCM register is a oscillator control register. It can control oscillator select, system mode, watchdog timer clock

source and rate.

OSCM initial value = 000x 000x

0CAH

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCM

WTCKS

WDRST

Wdrate

CPUM1

CPUM0

CLKMD

STPHX

R/W

Bit1

STPHX: External high-speed oscillator control bit.

0 = free run,

1 = stop.

Note: This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC

oscillator is still running.

Bit2

CLKMD: System high/Low speed mode select bit.

0 = normal (dual) mode,

1 = slow mode.

Bit[4:3] CPUM[1:0]: CPU operating mode control bit.

00 = normal,

01 = sleep (power down) mode,

10 = green mode,

11 = reserved.

Bit5

Wdrate: Watchdog timer rate select bit.

0 = Fcpu

÷ 214

1 = Fcpu

÷ 28

(The detail information is in watchdog timer chapter.)

Bit6

WDRST: Watchdog timer reset bit.

0 = Non reset,

1 = clear the watchdog timer’s counter.

(The detail information is in watchdog timer chapter.)

Bit7

WTCKS: Watchdog clock source select bit.

0 = Fcpu,

1 = internal RC low clock.

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