Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

9

©2001 Silicon Storage Technology, Inc.

S71135-02-000

4/01

380

TABLE

Address Inputs

1. If is forbidden for ROMCS# pin and RAMCS# pin to be “0” at the same time

RAMCS#1

WE#

OE#

XH

H

2. X means Don’t Care.

X2

Z

Standby

LH

X2

H

Z

Output Floating

LH

X2

L

Dout

ROM Read

H

L

H

H

Z

Output Floating

H

L

H

L

Dout

RAM Read

HL

L

H

Din

RAM Write

T8.4 380

Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among

RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high,

TWP is measured from the beginning of write to the end of write.

2. TCW is measured from the later of RAMCS# going low to the end of write.

3. TAS is measured from the address valid to the beginning of write.

4. TWR is measured from the end of write to the address change.

5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state.

Inputs of opposite phase of the output must not be applied because bus contention can occur.

6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.

7. DOUT is the same phase of the latest written data in this write cycle.

8. DOUT is the read data of new address

9. ROMCS# = VIH

TWC

TAW

TCW(2)

TOH

TDH

TDW

TOW

TWR(4)

Data Valid

380 ILL F07.0

Data In

Data Out

WE#

High-Z

High-Z (6)

(7)

(8)

Address

RAMCS#

TWP(1)

TAS(3)

TWHZ(5)