TLC320AD55CDW datasheet(20/41 Pages) TI1

Il numero della parte	TLC320AD55CDW

Spiegazioni elettronici	Sigma-Delta Analog Interface Circuit

PDF	41 Pages

Scroll/Zoom	100%

Produttore elettronici	TI1 [Texas Instruments]

Homepage	http://www.ti.com

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20 / 41 page

3–2

Figure 3–1 shows the timing relationship for SCLK, FS, DOUT and DIN in a primary communication. The

timing sequence for this operation is as follows:

The TLC320AD55C takes FS low.

One 16-bit word is transmitted from the ADC (DOUT) and one 16-bit word is received for the DAC

(DIN).

The TLC320AD55C takes FS high.

D15

D14

...D2

tdis

SCLK

tsu

td1

ten

D15

D14

...D2

DIN

DOUT

td2

In 16-Bit Mode:

MSB

tsu

D15

D14

...D2

DIN

In 16-Bit Mode:

MSB

LSB

td3

MCLK

0th

1st

2nd

14th

15th

16th

VIH

VIL

VOH

VOL

VOH

VOL

Figure 3–1. Primary Serial Communication Timing

When a secondary request is made through the LSB of the DAC data word (16-bit mode), the format shown

in Figure 3–2 is used:

D15

D14

D13

D12

D11

D10

15-bit DAC

2s-complement format

16-bit ADC

2s-complement format

control

Figure 3– 2. DAC and ADC Word Lengths

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