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TLC320AD55CDW Scheda tecnica(PDF) 21 Page - Texas Instruments |
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TLC320AD55CDW Scheda tecnica(HTML) 21 Page - Texas Instruments |
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21 / 41 page ![]() 3–3 3.2 Secondary Serial Communication Secondary serial communication reads or writes 16-bit words that program both the options and the circuit configurations of the device. All register programming occurs during secondary communications. Four primary and secondary communication cycles are required to program the four registers. When the default value for a particular register is desired, the user can omit addressing it during secondary communication. A no-op command addresses the no-op register (register 0), and no register programming takes place during this secondary communication. There are two methods for initiating secondary communications (see Figure 3–3): 1) by asserting a high level on FC, or 2) by asserting the LSB of DIN 16-bit serial communication high while not in 16-bit mode (see control 1 register bit 0). Secondary Request 16-Bit Mode (Control 1 Register, Bit 0) FC (Hardware) (LSB 0f DIN) Internal TLC320AD55C Figure 3– 3. Hardware and Software Methods to Initate a Secondary Request 1. Figures 3–5 and 3–6 show the two different methods by which FC requests secondary communication words as well as the timing for FS, DOUT, DIN, and SCLK. The examples span two primary communication frames. Figure 3–5 shows the use of hardware function control. During a secondary communication, a register can be written to or read from. When writing a value to a register, DIN contains the value to be written (see Figure 3–7). The data returned on DOUT is 00(hex). When performing a read function, DIN can still provide data to be written to an addressed register; however, DOUT contains the most recent value contained in the register addressed by DIN. DIN (Secondary Read) 8 Bits DIN (Secondary Write) 8 Bits R/W Register Address Don’t Care Data to the Register Figure 3– 4. Secondary DIN Format In Figure 3–5, FC clocks in and latches on the rising edge of frame sync (FS). This causes the start of the secondary update 32 FCLKs (see Fk divide register, Appendix A) after the start of the primary communication frame. Read and write examples are shown for DIN and DOUT. 2. Figure 3–6 shows the use of software function control. The software request for function control is typically used when the required resolution of the DAC channel is less than 16 bits. Then the least significant bit (D0) can be used for the secondary requests as shown in Table 3–1. |
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