TLC320AD55CDW datasheet(35/41 Pages) TI1

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A–1

Appendix A

Data bits D12 through D8 in the secondary serial communication contain the address of the register, and

data bits D7 through D0 contain the data that is to be written to the register. Data bit D13 determines a read

or write cycle to the addressed register. When data bit D13 is low, a write cycle is selected.

The following table shows the register map:

Table A– 1. Register Map

D15

D14

D13

D12

D11

D10

No operation

000000

Control 1

000001

Control 2

000001

Fk divide

000010

Fsclk divide

Control 3

Table A– 2. Control 1 Register

DESCRIPTION

–

Software reset

–

Software reset not asserted

–

Software power down (analog and filters)

–

Software power down (not asserted)

–

Select AUXP and AUXM

–

Select INP and INM

–

Analog output gain = 1

–

Analog output gain = 1/2

–

Analog output gain = 1/4

–

Analog output gain = 0 (squelch)

–

Analog loopback asserted

–

Analog loopback not asserted

–

Digital loopback asserted

–

Digital loopback not asserted

–

16-bit mode (hardware secondary requests)

–

Not 16-bit mode (software secondary requests)

Default register value: 00000000

The software reset is a one-shot operation and this bit is cleared to zero after reset. It is not necessary to

write a zero to end the master reset operation.

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