CXP87452 datasheet(18/32 Pages) SONY

18 / 32 page

– 18 –

CXP87452/87460

Input mode

Output mode

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

Chip select transfer mode

(SCK = output mode)

Chip select transfer mode

(SCK = output mode)

Chip select transfer mode

Note 1)

tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO means each pin of CS

→ CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0)

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

↓→ SCK

delay time

↑→ SCK

floating delay time

↓→ SO

delay time

↓→ SO

floating delay time

high level width

SCK

cycle time

SCK

high and low level widths

SI input setup time

(against SCK

↑)

SI input hold time

(against SCK

↑)

SCK

↓→ SO delay time

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH

tKL

tSIK

tKSI

tKSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Symbol

Min.

tsys + 200

8000/fc

tsys + 100

8000/fc – 100

–

tsys + 100

200

tsys + 100

100

tsys + 200

100

Max.

Unit

Condition

CXP87452 Scheda tecnica(PDF) 18 Page - Sony Corporation

CXP87452 Scheda tecnica(HTML) 18 Page - Sony Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Scheda tecnica Scarica

Link URL