Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

Preview PDF HTML

CXP87452 Scheda tecnica(PDF) 21 Page - Sony Corporation

Il numero della parte CXP87452
Spiegazioni elettronici  CMOS 8-bit Single Chip Microcomputer
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  SONY [Sony Corporation]
Homepage  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXP87452 Scheda tecnica(HTML) 21 Page - Sony Corporation

Back Button CXP87452 Datasheet HTML 17Page - Sony Corporation CXP87452 Datasheet HTML 18Page - Sony Corporation CXP87452 Datasheet HTML 19Page - Sony Corporation CXP87452 Datasheet HTML 20Page - Sony Corporation CXP87452 Datasheet HTML 21Page - Sony Corporation CXP87452 Datasheet HTML 22Page - Sony Corporation CXP87452 Datasheet HTML 23Page - Sony Corporation CXP87452 Datasheet HTML 24Page - Sony Corporation CXP87452 Datasheet HTML 25Page - Sony Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 32 page
background image
– 21 –
CXP87452/87460
Serial transfer (CH1) (SIO mode)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Min.
Max.
Unit
Condition
SCK1 cycle time
SCK1 high and low
level widths
SI1 input setup time
(against SCK1
↑)
SI1 input hold time
(against SCK1
↑)
SCK1
↓→ SO1 delay time
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
2
tsys + 200
16000/fc
tsys + 100
8000/fc – 100
100
200
tsys + 200
100
tsys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1)
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1) (SIO mode)
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Item
Symbol
Pin
Min.
Max.
Unit
Condition
SCK1 cycle time
SCK1 high and low
level widths
SI1 input setup time
(against SCK1
↑)
SI1 input hold time
(against SCK1
↑)
SCK1
↓→ SO1 delay time
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
2
tsys + 200
16000/fc
tsys + 100
8000/fc – 150
100
200
tsys + 200
100
tsys + 250
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1)
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com