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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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PCAL9554CBS Scheda tecnica(PDF) 16 Page - NXP Semiconductors |
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PCAL9554CBS Scheda tecnica(HTML) 16 Page - NXP Semiconductors |
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16 / 42 page  PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 10 December 2012 16 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 8.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad. Figure 15 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the current control register. When the Current Control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50 %. Fig 13. High value resistor in parallel with the LED Fig 14. Device supplied by a lower voltage 002aag164 LED VDD Pn 100 kΩ VDD 002aag165 LED VDD Pn 3.3 V 5 V Fig 15. Simplified output stage VDD P0 to P7 Configuration register 002aah108 DECODER PMOS_EN0 PMOS_EN1 PMOS_EN2 PMOS_EN3 NMOS_EN3 NMOS_EN2 NMOS_EN1 NMOS_EN0 Output port register Current Control register PMOS_EN[3:0] NMOS_EN[3:0] |
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