PCAL9554CBS datasheet(12/42 Pages) NXP

12 / 42 page

PCAL9554B_PCAL9554C

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Product data sheet

Rev. 2 — 10 December 2012

12 of 42

NXP Semiconductors

PCAL9554B; PCAL9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

Bus transactions

The PCAL9554B/PCAL9554C is an I2C-bus slave device. Data is exchanged between the

master and PCAL9554B/PCAL9554C through write and read commands using I2C-bus.

The two communication lines are a serial data line (SDA) and a serial clock line (SCL).

Both lines must be connected to a positive supply via a pull-up resistor when connected to

the output stages of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Write commands

Data is transmitted to the PCAL9554B/PCAL9554C by sending the device address and

setting the Least Significant Bit (LSB) to a logic 0 (see Figure 4 for device address). The

command byte is sent after the address and determines which register receives the data

that follows the command byte. There is no limitation on the number of data bytes sent in

one write transmission.

(1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0.

Fig 7.

Write to Output port register

slave address(1)

START condition

R/W

acknowledge

from slave

002aah124

0000001

command byte

acknowledge

from slave

12345678

SCL

SDA

DATA 1

write to port

data out from port

tv(Q)

acknowledge

from slave

DATA 1 VALID

data to port

A2 A1 A0

STOP

condition

(1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0.

Fig 8.

Write to Configuration or Polarity inversion registers

slave address(1)

START condition

R/W

acknowledge

from slave

002aah125

0 1/0 1/0

command byte

acknowledge

from slave

12345678

SCL

SDA

DATA 1

acknowledge

from slave

data to register

A2 A1 A0

STOP

condition

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