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PCAL9554CBS Scheda tecnica(PDF) 29 Page - NXP Semiconductors |
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PCAL9554CBS Scheda tecnica(HTML) 29 Page - NXP Semiconductors |
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29 / 42 page ![]() PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 10 December 2012 29 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 14. Parameter measurement information a. SDA load configuration b. Transaction format c. Voltage waveforms CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z o =50 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data. (1) See Figure 9. Fig 29. I2C-bus interface load circuit and voltage waveforms 002aag803 DUT CL = 50 pF RL = 1 kΩ SDA VDD STOP condition (P) Data Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) R/W Bit 0 (LSB) Address Bit 1 Address Bit 7 (MSB) START condition (S) STOP condition (P) two bytes for read Input port register(1) 002aag952 tLOW tHIGH tr tf 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD tSP tBUF tf tHD;STA tr SCL SDA tSU;DAT tHD;DAT tf(o) tVD;ACK tVD;DAT tVD;ACK tSU;STA tSU;STO 002aag804 repeat START condition STOP condition |
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