MC68331MFC16 datasheet(77/84 Pages) FREESCALE

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MC68331TS/D

PAMOD — Pulse Accumulator Mode

0 = External event counting

1 = Gated time accumulation

PEDGE — Pulse Accumulator Edge Control

The effects of PEDGE and PAMOD are shown in the following table.

PCLKS — PCLK Pin State (Read Only)

I4/O5 — Input Capture 4/Output Compare 5

0 = Output compare 5 enabled

1 = Input capture 4 enabled

PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)

PACNT — Pulse Accumulator Counter

8-bit read/write counter used for external event counting or gated time accumulation.

TIC[1:3] — Input Capture Registers 1–3

$YFF90E, $YFF910, $YFF912

The input capture registers are 16-bit read-only registers which are used to latch the value of TCNT

when a specified transition is detected on the corresponding input capture pin. They are reset to $FFFF.

TOC[1:4] — Output Compare Registers 1–4

$YFF914, $YFF916, $YFF918, $YFF91A

The output compare registers are 16-bit read/write registers which can be used as output waveform

controls or as elapsed time indicators. For output compare functions, they are written to a desired match

value and compared against TCNT to control specified pin actions. They are reset to $FFFF.

TI4/O5 — Input Capture 4/Output Compare 5 Register

$YFF91C

This register serves either as input capture register 4 or output compare register 5, depending on the

state of I4/O5 in PACTL.

TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of input

capture to be performed.

PAMOD

PEDGE

Effect

PAI falling edge increments counter

PAI rising edge increments counter

Zero on PAI inhibits counting

One on PAI inhibits counting

PACLK[1:0]

Pulse Accumulator Clock Selected

System Clock Divided by 512

Same Clock Used to Increment TCNT

TOF Flag from TCNT

External Clock, PCLK

TCTL1/TCTL2 — Timer Control Registers 1–2

$YFF91E

OM5

OL5

OM4

OL4

OM3

OL3

OM2

OL2

EDGE4

EDGE3

EDGE2

EDGE1

RESET:

Freescale Semiconductor, Inc.

For More Information On This Product,

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