MC68331MFC16 datasheet(18/84 Pages) FREESCALE

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MC68331TS/D

SLVEN —Factory Test Mode Enabled

This bit is a read-only status bit that reflects the state of DATA11 during reset.

0 = IMB is not available to an external master.

1 = An external bus master has direct access to the IMB.

SHEN[1:0] —Show Cycle Enable

This field determines what the EBI does with the external bus during internal transfer operations. A

show cycle allows internal transfers to be externally monitored. The table below shows whether show

cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,

external peripherals must not be enabled during show cycles.

SUPV —Supervisor/Unrestricted Data Space

The SUPV bit places the SIM global registers in either supervisor or user data space.

0 = Registers with access controlled by the SUPV bit are accessible from either the user or super-

visor privilege level.

1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.

MM —Module Mapping

0 = Internal modules are addressed from $7FF000 –$7FFFFF.

1 = Internal modules are addressed from $FFF000 –$FFFFFF.

IARB[3:0] —Interrupt Arbitration Field

Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration

between interrupt requests of the same priority is performed by serial contention between IARB field bit

values. Contention must take place whenever an interrupt request is acknowledged, even when there

is only a single pending request. An IARB field must have a non-zero value for contention to take place.

If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU pro-

cesses a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU,

the SIM IARB field value is used for arbitration between internal and external interrupts of the same pri-

ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is

%0000, which prevents SIM interrupts from being discarded during initialization.

3.2.2 System Protection Control Register

The system protection control register controls system monitor functions, software watchdog clock

prescaling, and bus monitor timing. This register can be written only once following power-on or reset,

but can be read at any time.

SWE —Software Watchdog Enable

0 = Software watchdog disabled

1 = Software watchdog enabled

SHEN

Action

Show cycles disabled, external arbitration enabled

Show cycles enabled, external arbitration disabled

Show cycles enabled, external arbitration enabled

Show cycles enabled, external arbitration enabled,

internal activity is halted by a bus grant

SYPCR —System Protection Control Register

$YFFA21

NOT USED

SWE

SWP

SWT

HME

BME

BMT

RESET:

MODCLK

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