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JS28F256P33BFE Scheda tecnica(PDF) 39 Page - Micron Technology

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Datasheet
Aug 2009
39
Order Number:320003-08
P33-65nm
11.1.6
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
11.1.7
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 15 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
Table 14: WAIT Functionality Table
Condition
WAIT
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
High-Z
1
CE# =’0’, OE# = ‘0’
Active
1
Synchronous Array Reads
Active
1
Synchronous Non-Array Reads
Active
1
All Asynchronous Reads
Deasserted
1
All Writes
High-Z
1,2
Notes:
1.
Active: WAIT is asserted until data becomes valid, then deasserts.
2.
When OE# = VIH during writes, WAIT = High-Z.
Table 15: Burst Sequence Word Ordering (Sheet 1 of 2)
Start
Addr.
(DEC)
Burst
Wrap
(RCR.3)
Burst Addressing Sequence (DEC)
4-Word Burst
(BL[2:0] = 0b001)
8-Word Burst
(BL[2:0] = 0b010)
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
0
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
1
0
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5…15-0
1-2-3-4-5-6-7-…
2
0
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6…15-0-1
2-3-4-5-6-7-8-…
3
0
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7…15-0-1-2
3-4-5-6-7-8-9-…
40
4-5-6-7-0-1-2-3
4-5-6-7-8…15-0-1-2-3
4-5-6-7-8-9-10…
50
5-6-7-0-1-2-3-4
5-6-7-8-9…15-0-1-2-3-
4
5-6-7-8-9-10-11…
60
6-7-0-1-2-3-4-5
6-7-8-9-10…15-0-1-2-
3-4-5
6-7-8-9-10-11-12-…
70
7-0-1-2-3-4-5-6
7-8-9-10…15-0-1-2-3-
4-5-6
7-8-9-10-11-12-13…
14
0
14-15-0-1-2…12-13
14-15-16-17-18-19-20-
…
15
0
15-0-1-2-3…13-14
15-16-17-18-19-20-21-
…



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