CDPCLK0 datasheet(56/274 Pages) ALTERA

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Chapter 4: Embedded Multipliers in the Cyclone III Device Family

Architecture

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Figure 4–2 shows the multiplier block architecture.

Input Registers

You can send each multiplier input signal into an input register or directly into the

multiplier in 9- or 18-bit sections, depending on the operational mode of the

multiplier. Each multiplier input signal can be sent through a register independently

of other input signals. For example, you can send the multiplier Data A signal through

a register and send the Data B signal directly to the multiplier.

The following control signals are available to each input register in the embedded

multiplier:

■

clock

■

clock enable

■

asynchronous clear

All input and output registers in a single embedded multiplier are fed by the same

clock, clock enable, and asynchronous clear signals.

Multiplier Stage

The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18

multipliers as well as other multipliers in between these configurations. Depending

on the data width or operational mode of the multiplier, a single embedded multiplier

can perform one or two multiplications in parallel. For multiplier information, refer to

“Operational Modes” on page 4–5.

Each multiplier operand is a unique signed or unsigned number. Two signals, signa

and signb, control an input of a multiplier and determine if the value is signed or

unsigned. If the signa signal is high, the Data A operand is a signed number. If the

signa

signal is low, the Data A operand is an unsigned number.

Figure 4–2. Multiplier Block Architecture

CLRN

ENA

Data A

Data B

aclr

clock

ena

signa

signb

CLRN

ENA

CLRN

ENA

Data Out

Embedded Multiplier Block

Output

Input

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