CDPCLK0 datasheet(85/274 Pages) ALTERA

85 / 274 page

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–25

PLL Cascading

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 5–19 shows using GCLK while cascading PLLs.

Consider the following guidelines when cascading PLLs:

■

Set the primary PLL to low bandwidth to help filter jitter. Set the secondary PLL to

high bandwidth to be able to track the jitter from the primary PLL. You can view

the Quartus II software compilation report file to ensure the PLL bandwidth

ranges do not overlap. If the bandwidth ranges overlap, jitter peaking can occur in

the cascaded PLL scheme.

1 You can get an estimate of the PLL deterministic jitter and static phase error

(SPE) by using the TimeQuest Timing Analyzer in the Quartus II software.

Use the SDC command "derive_clock_uncertainty" to direct TimeQuest to

generate a report titled "PLLJ_PLLSPE_INFO.txt" in your project directory.

Then, use "set_clock_uncertainty" commands to add jitter and SPE values to

your clock constraints.

Figure 5–19. PLL Cascading Using GCLK

CLK[0..3]

CLK[8..11]

GCLK[0..4]

GCLK[5..9]

GCLK[15..19]

GCLK[10..14]

CLK[12..15]

CLK[4..7]

Output from PLL

Input to PLL

Output from PLL

Five Clock

Control Blocks

Five Clock

Control Blocks

Five Clock

Control Blocks

Five Clock

Control Blocks

PLL

Remote clock

from two Clock

pins at adjacent

edge of device

GCLK[0:19]

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