CDPCLK0 datasheet(40/274 Pages) ALTERA

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3–6

Chapter 3: Memory Blocks in the Cyclone III Device Family

Overview

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

The address clock enable is typically used to improve the effectiveness of cache

memory applications during a cache-miss. The default value for the address clock

enable signals is low.

Figure 3–4 and Figure 3–5 show the address clock enable waveform during read and

write cycles, respectively.

Mixed-Width Support

M9K memory blocks support mixed data widths. When using simple dual-port, true

dual-port, or FIFO modes, mixed width support allows you to read and write

different data widths to an M9K memory block. For more information about the

different widths supported per memory mode, refer to “Memory Modes” on

page 3–7.

Figure 3–4. Cyclone III Device Family Address Clock Enable During Read Cycle Waveform

Figure 3–5. Cyclone III Device Family Address Clock Enable During Write Cycle Waveform

inclock

rden

rdaddress

q (synch)

q (asynch)

latched address

(inside memory)

dout0

dout1

dout4

dout1

dout4

dout5

addressstall

doutn-1

dout1

doutn

dout1

dout0

dout1

inclock

wren

wraddress

latched address

(inside memory)

addressstall

data

contents at a0

contents at a1

contents at a2

contents at a3

contents at a4

contents at a5

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