CDPCLK1 datasheet(90/274 Pages) ALTERA

90 / 274 page

5–30

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

PLL Reconfiguration

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

Figure 5–23 shows the scan chain bit order sequence for one PLL post-scale counter in

Cyclone III device family PLLs.

f For more information about the PLL scan chain, refer to the Implementing PLL

Reconfiguration in Cyclone III Devices application note.

Charge Pump and Loop Filter

You can reconfigure the charge pump and loop filter settings to update the PLL

bandwidth in real time. Table 5–5 through Table 5–7 list the possible settings for

charge pump (ICP), loop filter resistor (R), and capacitor (C) values for Cyclone III

device family PLLs.

Figure 5–23. Scan Chain Bit Order

DATAIN

rbypass

rselodd

DATAOUT

Table 5–5. Charge Pump Bit Control

CP[2]

CP[1]

CP[0]

Setting (Decimal)

0000

0011

0113

1117

Table 5–6. Loop Filter Resistor Value Control

LFR[4]

LFR[3]

LFR[2]

LFR[1]

LFR[0]

Setting

(Decimal)

000

113

001

004

010

008

100

101

110

111

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