CDPCLK1 datasheet(36/274 Pages) ALTERA

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Chapter 3: Memory Blocks in the Cyclone III Device Family

Overview

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Table 3–1 lists the features supported by the M9K memory

f For information about the number of M9K memory blocks for the Cyclone III device

family, refer to the Cyclone III Device Family Overview chapter.

Table 3–1. Summary of M9K Memory Features

Feature

M9K Blocks

Configurations (depth × width)

8192 × 1

4096 × 2

2048 × 4

1024 × 8

1024 × 9

512 × 16

512 × 18

256 × 32

256 × 36

Parity bits

Byte enable

Packed mode

Address clock enable

Single-port mode

Simple dual-port mode

True dual-port mode

Embedded shift register mode (1)

ROM mode

FIFO buffer (1)

Simple dual-port mixed width support

True dual-port mixed width support (2)

Memory initialization file (.mif)

Mixed-clock mode

Power-up condition

Outputs cleared

Read address registers and output registers only

Latch asynchronous clears

Output latches only

Write or read operation triggering

Write and read: Rising clock edges

Same-port read-during-write

Outputs set to Old Data or New Data

Mixed-port read-during-write

Outputs set to Old Data or Don’t Care

Notes to Table 3–1:

(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control

logic.

(2) Width modes of ×32 and ×36 are not available.

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