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PCIF0 Scheda tecnica(PDF) 26 Page - ATMEL Corporation

Il numero della parte PCIF0
Spiegazioni elettronici  High Performance, Low Power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture
PDF  294 Pages
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Produttore elettronici  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

PCIF0 Scheda tecnica(HTML) 26 Page - ATMEL Corporation

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26
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
• Bit 7:1 – Reserved Bits
These bits are reserved for future use and will always read as 0 in Atmel
® AVR®.
• Bits 8:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM
address in the EEPROM space (see “E2 size” in Table 3-1 on page 19). The EEPROM data
bytes are addressed linearly between 0 and “E2 size”. The initial value of EEAR is undefined.
A proper value must be written before the EEPROM may be accessed.
Note:
For information only - ATtiny47: EEAR8 exists as register bit but it is not used for addressing.
3.5.2
EEDR – EEPROM Data Register
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
3.5.3
EECR – EEPROM Control Register
• Bit 7,6 – Res: Reserved Bits
These bits are reserved for future use and will always read as 0 in the Atmel AVR. After read-
ing, mask out these bits. For compatibility with future Atmel AVR devices, always write these
bits to zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase the
old value and program the new value) or to split the Erase and Write operations in two differ-
ent operations. The Programming times for the different modes are shown in Table 3-2. While
EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to
0b00 unless the EEPROM is busy programming.
Bit
7
6
543210
EEDR7
EEDR6
EEDR5
EEDR4
EEDR3
EEDR2
EEDR1
EEDR0
EEDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
000000
Bit
7
6
543210
–
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
EECR
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
X
X
0
0
X
0
Table 3-2.
EEPROM Mode Bits
EEPM1
EEPM0
Typical
Programming Time Operation
0
0
3.4ms
Erase and Write in one operation (Atomic Operation)
0
1
1.8ms
Erase Only
1
0
1.8ms
Write Only
1
1
–
Reserved for future use



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