PCIF0 datasheet(43/294 Pages) ATMEL

43 / 294 page

9219A–RFID–01/11

Atmel ATA5505 [Preliminary]

4.5.3

CLKCSR – Clock Control & Status Register

• Bit 7 – CLKCCE: Clock Control Change Enable

The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The

CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to

zero. CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits

are written. Rewriting the CLKCCE bit within this time-out period does neither extend the

time-out period, nor clear the CLKCCE bit.

• Bits 6:5 – Res: Reserved Bits

These bits are reserved bits in the Atmel® AVR® and will always read as zero.

• Bits 4 – CLKRDY: Clock Ready Flag

This flag is the output of the ‘Clock Availability ’ logic.

This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’

command being entered.

Table 4-10.

Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

000

001

010

011

128

100

256

Reserved

Bit

3210

CLKCCE

–

CLKRDY

CLKC3

CLKC2

CLKC1

CLKC0

CLKCSR

Read/Write

R/W

Initial Value

0000

PCIF0 Scheda tecnica(PDF) 43 Page - ATMEL Corporation

PCIF0 Scheda tecnica(HTML) 43 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL