AD9753ASTRL datasheet(10/28 Pages) AD

10 / 28 page

REV. B

–10–

AD9753

IOUTA

IOUTB

SEGMENTED

SWITCHES FOR

DB0 TO DB11

DAC

FSADJ

REFIO

1.2V REF

DIV0

PLLLOCK

DIGITAL DATA INPUTS

0.1 F

RSET

RLOAD

DB0 – DB11

DCOM

PMOS CURRENT

SOURCE ARRAY

AVDD

3.0V TO 3.6V

DVDD

2–1 MUX

PORT 1 LATCH

DAC LATCH

ACOM

PORT 2 LATCH

DIV1

PLL

CIRCUITRY

PLLVDD

CLKVDD

CLK+

CLK–

CLKCOM

RESET

LPF

DB0 – DB11

VOUTB

RLOAD

VOUTA

VDIFF = VOUTA – VOUTB

Figure 3. Simplified Block Diagram

FUNCTIONAL DESCRIPTION

Figure 3 shows a simplified block diagram of the AD9753. The

AD9753 consists of a PMOS current source array capable of

providing up to 20 mA of full-scale current, IOUTFS. The

array is divided into 31 equal sources that make up the five

most significant bits (MSBs). The next four bits, or middle bits,

consist of 15 equal current sources whose value is 1/16th of an

MSB current source. The remaining LSBs are a binary weighted

fraction of the middle bit current sources. Implementing the

middle and lower bits with current sources, instead of an R-2R

ladder, enhances dynamic performance for multitone or low

amplitude signals and helps maintain the DAC’s high output

impedance (i.e., >100 k

Ω).

All of the current sources are switched to one of the two

outputs (i.e., IOUTA or IOUTB) via PMOS differential current

switches. The switches are based on a new architecture that

drastically improves distortion performance. This new switch

architecture reduces various timing errors and provides matching

complementary drive signals to the inputs of the differential

current switches.

The analog and digital sections of the AD9753 have separate

power supply inputs (i.e., AVDD and DVDD) that can operate

independently over a 3.0 V to 3.6 V range. The digital section,

which is capable of operating at a 300 MSPS clock rate, consists

of edge-triggered latches and segment decoding logic circuitry.

The analog section includes the PMOS current sources, the

associated differential switches, a 1.20 V band gap voltage refer-

ence, and a reference control amplifier.

The full-scale output current is regulated by the reference control

amplifier and can be set from 2 mA to 20 mA via an external

resistor, RSET. The external resistor, in combination with both

the reference control amplifier and voltage reference VREFIO, sets

the reference current IREF, which is replicated to the segmented

current sources with the proper scaling factor. The full-scale

current, IOUTFS, is 32 times the value of IREF.

REFERENCE OPERATION

The AD9753 contains an internal 1.20 V band gap reference.

This can easily be overdriven by an external reference with no

effect on performance. REFIO serves as either an input or output,

depending on whether the internal or an external reference is

used. To use the internal reference, simply decouple the REFIO

pin to ACOM with a 0.1

µF capacitor. The internal reference

voltage will be present at REFIO. If the voltage at REFIO is to

be used elsewhere in the circuit, an external buffer amplifier

with an input bias current less than 100 nA should be used. An

example of the use of the internal reference is given in Figure 4.

A low impedance external reference can be applied to REFIO,

as shown in Figure 5. The external reference may provide either

a fixed reference voltage to enhance accuracy and drift perfor-

mance or a varying reference voltage for gain control. Note

that the 0.1

µF compensation capacitor is not required since

the internal reference is overdriven, and the relatively high input

impedance of REFIO minimizes any loading of the external

reference.

1.2V REF

AVDD

IREF

CURRENT

SOURCE

ARRAY

REFIO

FSADJ

0.1 F

AD9753

REFERENCE

SECTION

ADDITIONAL

EXTERNAL

LOAD

OPTIONAL

EXTERNAL

REFERENCE

BUFFER

Figure 4. Internal Reference Configuration

1.2V REF

AVDD

IREF

CURRENT

SOURCE

ARRAY

REFIO

FSADJ

AD9753

REFERENCE

SECTION

EXTERNAL

REFERENCE

AVDD

Figure 5. External Reference Configuration

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