AD9753ASTRL datasheet(12/28 Pages) AD

12 / 28 page

REV. B

–12–

AD9753

reference clock that is twice the input data rate should consider

disabling the PLL clock multiplier to achieve the best SNR

performance from the AD9753. Note, the SFDR performance

of the AD9753 remains unaffected with or without the PLL

clock multiplier enabled.

The effects of phase noise on the AD9753’s SNR performance

become more noticeable at higher reconstructed output frequen-

cies and signal levels. Figure 8 compares the phase noise of a

full-scale sine wave at exactly fDATA/4 at different data rates

(thus carrier frequency) with the optimum DIV1, DIV0 setting.

SNR is partly a function of the jitter generated by the clock

circuitry. As a result, any noise on PLLVDD or CLKVDD may

decrease the SNR at the output of the DAC. To minimize this

potential problem, PLLVDD and CLKVDD can be connected

to DVDD using an LC filter network similar to the one shown

in Figure 9.

FREQUENCY OFFSET (MHz)

–20

–110

–10

–30

–40

–50

–60

–70

–80

–90

–100

234

PLL ON, fDATA = 150MSPS

PLL OFF, fDATA = 50MSPS

Figure 8. Phase Noise of PLL Clock Multiplier at

fOUT = fDATA/4 at Different fDATA Settings with DIV0/DIV1

Optimized, Using R&S FSEA30 Spectrum Analyzer

100 F

ELECT.

10 F

TANT.

0.1 F

CER.

TTL/CMOS

LOGIC

CIRCUITS

3.3V POWER SUPPLY

FERRITE

BEADS

CLKVDD

PLLVDD

CLKCOM

Figure 9. LC Network for Power Filtering

DAC TIMING WITH PLL ACTIVE

As described in Figure 7, in PLL active mode, Port 1 and

Port 2 input latches are updated on the rising edge of CLK. On

the same rising edge, data previously present in the input Port 2

latch is written to the DAC output latch. The DAC output will

update after a short propagation delay (tPD).

Following the rising edge of CLK at a time equal to half of its

period, the data in the Port 1 latch will be written to the DAC

output latch, again with a corresponding change in the DAC

output. Due to the internal PLL, the time at which the data in

the Port 1 and Port 2 input latches is written to the DAC latch

is independent of the duty cycle of CLK. When using the PLL,

the external clock can be operated at any duty cycle that meets

the specified input pulsewidth.

On the next rising edge of CLK, the cycle begins again with the

two input port latches being updated, and the DAC output latch

being updated with the current data in the Port 2 input latch.

PLL DISABLED MODE

When PLLVDD is grounded, the PLL is disabled. An external

clock must now drive the CLK inputs at the desired DAC out-

put update rate. The speed and timing of the data present at

input Ports 1 and 2 are now dependent on whether or not the

AD9753 is interleaving the digital input data or only responding

to data on a single port. Figure 10 is a functional block diagram

of the AD9753 clock control circuitry with the PLL disabled.

PLLVDD

TO DAC

LATCH

PLLLOCK

CLOCK

LOGIC

( 1 OR

DIFFERENTIAL-

TO-

SINGLE-ENDED

AMP

INTERNAL

MUX

CLKIN+

CLKIN–

AD9753

RESET DIV0 DIV1

TO INPUT

LATCHES

Figure 10. Clock Circuitry with PLL Disabled

DIV0 and DIV1 no longer control the PLL but are used to set

the control on the input mux for either interleaving or non-

interleaving the input data. The different modes for states of

DIV0 and DIV1 are given in Table II.

Table II. Input Mode for DIV0,

DIV1 Levels with PLL Disabled

Input Mode

DIV1

DIV0

Interleaved (2

×)0

Noninterleaved

Port 1 Selected

Port 2 Selected

Not Allowed

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