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IR21141SS Scheda tecnica(PDF) 21 Page - International Rectifier |
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IR21141SS Scheda tecnica(HTML) 21 Page - International Rectifier |
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21 / 34 page ![]() IR21141/IR22141SSPbF www.irf.com © 2009 International Rectifier 21 3 PCB Layout Tips 3.1 Distance from High to Low Voltage The IR2x14x pinout maximizes the distance between floating (from DC- to DC+) and low voltage pins. It’s strongly recommended to place components tied to floating voltage on the high voltage side of device (VB, VS side) while the other components are placed on the opposite side. 3.2 Ground Plane To minimize noise coupling, the ground plane must not be placed under or near the high voltage floating side. 3.3 Gate Drive Loops Current loops behave like antennas and are able to receive and transmit EM noise. In order to reduce the EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Figure 23 shows the high and low side gate loops. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, increasing the possibility of self turn-on. For this reason, it is strongly recommended to place the three gate resistances close together and to minimize the loop area (see Fig. 23). gate resistance VS/COM VB/ VCC H/LOP H/LON SSDH/L VGE Gate Drive Loop CGC IGC Figure 23: gate drive loop 3.4 Supply Capacitors The IR2x14x output stages are able to quickly turn on an IGBT, with up to 2 A of output current. The supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic inductance/resistance. 3.5 Routing and Placement Example Figure 24 shows one of the possible layout solutions using a 3 layer PCB. This example takes into account all the previous considerations. Placement and routing for supply capacitors and gate resistances in the high and low voltage side minimize the supply path loop and the gate drive loop. The bootstrap diode is placed under the device to have the cathode as close as possible to the bootstrap capacitor and the anode far from high voltage and close to VCC. R2 R3 R4 R5 R6 R7 C2 D3 D2 IR2214 VGH VGL DC+ Phase a) Top Layer R1 C1 VEH VEL VCC b) Bottom Layer c) Ground Plane Figure 24: layout example Information below refers to Fig. 24: Bootstrap section: R1, C1, D1 High side gate: R2, R3, R4 High side Desat: D2 Low side supply: C2 Low side gate: R5, R6, R7 Low side Desat: D3 |
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