IR21141SS datasheet(13/34 Pages) IRF

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IR21141/IR22141SSPbF

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Figure 13:

High and Low Side Output Stage

FLTCLR

SET

CLR

FAULT/SD

SY_FLT

internal

HOLD

(external

hold)

(external hard

shutdown)

internal FAULT

(hard shutdown)

UVCC

DesatHS

DesatLS

Figure 14:

Fault Management Diagram

The external sensing diode should have breakdown

voltage greater than 600 V (IR21141) or 1200 V

(IR22141), and low stray capacitance (in order to

minimize noise coupling and switching delays). The

diode is biased by an internal pull-up resistor RDSH/L

(equal to VCC/IDS- or VBS/IDS-) or by a dedicated circuit

(see the active-bias section). To limit the current flowing

through DSH and DSL in case of desaturation an

external Schottky diode is required, as shown in Fig. 13.

When VCE increases, the voltage at the DSH or DSL pin

increases too. Being internally biased to the local supply,

the DSH/DSL voltage is automatically clamped. When

DSH/DSL

exceeds

the

VDESAT+

threshold,

the

comparator triggers (see Fig. 13). The comparator’s

output is filtered in order to avoid false desaturation

detection by externally induced noise; pulses shorter

than tDS are filtered out. To avoid detecting a false

desaturation event during IGBT turn on, the desaturation

circuit is disabled by a blanking signal (TBL, see blanking

block in Fig. 13). This time is the estimated maximum

IGBT turn on time and must be not exceeded by proper

gate resistance sizing. When the IGBT is not completely

saturated after TBL, desaturation is detected and the

driver will turn off.

Eligible desaturation signals initiate the SSD sequence.

While in SSD, the driver’s output goes to a high

impedance state and the SSD pull-down is activated to

turn off the IGBT through the SSDH/SSDL pin. The

SY_FLT output pin (active low, see Fig. 14) reports the

gate driver status during the SSD sequence (tSS). Once

the SSD has finished, SY_FLT releases, and the gate

driver generates a FAULT signal (see the FAULT/SD

section) by activating the FAULT/SD pin. This generates

a hard shutdown for both the high and low output stages

(HO=LO=low). Each driver is latched low until the fault is

cleared (see FLT_CLR).

Figure 14 shows the fault management circuit. In this

diagram DesatHS and DesatLS are two internal signals

that come from the output stages (see Fig. 13).

It must be noted that while in SSD, both the

undervoltage fault and external SD are masked until the

end

SSD.

Desaturation

protection

working

independently by the other control pin and it is disabled

only when the output status is off.

1.4.4 Fault Management in Multi-Phase Systems

In a system with two or more gate drivers the

IR21141/IR22141 devices must be connected as shown

in Fig. 15.

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