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PIC16F628A-IP Scheda tecnica(PDF) 24 Page - Microchip Technology

Il numero della parte PIC16F628A-IP
Spiegazioni elettronici  Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
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Produttore elettronici  MICROCHIP [Microchip Technology]
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PIC16F627A/628A/648A
DS40044G-page 24
© 2009 Microchip Technology Inc.
4.2.2.1
Status Register
The Status register, shown in Register 4-1, contains the
arithmetic status of the ALU; the Reset status and the
bank select bits for data memory (SRAM).
The Status register can be the destination for any
instruction, like any other register. If the Status register
is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are non-
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the Status register
as “000uu1uu” (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF
and MOVWF instructions are used to alter the
Status register because these instructions do not affect
any Status bit. For other instructions, not affecting any
Status bits, see the “Instruction Set Summary”.
REGISTER 4-1:
STATUS – STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
Note:
The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
ZDC
C
bit 7
bit 0
bit 7
IRP
: Register Bank Select bit (used for indirect addressing)
1
= Bank 2, 3 (100h-1FFh)
0
= Bank 0, 1 (00h-FFh)
bit 6-5
RP<1:0>
: Register Bank Select bits (used for direct addressing)
00
= Bank 0 (00h-7Fh)
01
= Bank 1 (80h-FFh)
10
= Bank 2 (100h-17Fh)
11
= Bank 3 (180h-1FFh)
bit 4
TO
: Time Out bit
1
= After power-up, CLRWDT instruction or SLEEP instruction
0
= A WDT time out occurred
bit 3
PD
: Power-down bit
1
= After power-up or by the CLRWDT instruction
0
= By execution of the SLEEP instruction
bit 2
Z
: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
bit 1
DC
: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for Borrow the polarity
is reversed)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
bit 0
C
: Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result occurred
Note:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown



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