PIC16F628A-IP datasheet(89/180 Pages) MICROCHIP

89 / 180 page

DS40044G-page 89

PIC16F627A/628A/648A

FIGURE 12-10:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

12.5

USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RB2/TX/CK pin (instead of being supplied internally

in Master mode). This allows the device to transfer or

receive data while in Sleep mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

12.5.1

USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical except in the case of the Sleep

mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The first word will immediately transfer to the

TSR register and transmit.

The second word will remain in TXREG register.

Flag bit TXIF will not be set.

When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set.

If enable bit TXIE is set, the interrupt will wake

the chip from Sleep and if the global interrupt is

enabled, the program will branch to the interrupt

vector (0004h).

Follow these steps when setting up a Synchronous

Slave Transmission:

TRISB<1> and TRISB<2> should both be set to

‘1’ to configure the RB1/RX/DT and RB2/TX/CK

pins as inputs. Output drive, when required, is

controlled by the peripheral circuitry.

Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

Clear bits CREN and SREN.

If interrupts are desired, then set enable bit

TXIE.

If 9-bit transmission is desired, then set bit TX9.

Enable the transmission by setting enable bit

TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

CREN bit

RB1/RX/DT pin

RB2/TX/CK pin

WRITE to

Bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4

Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4

‘0’

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

‘0’

Q1Q2Q3Q4

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.

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