R5F564MLGDLC datasheet(50/67 Pages) RENESAS

50 / 67 page

RX64M Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0173EJ0090 Rev.0.90

Page 50 of 67

Feb 28, 2014

TRDATA2

P54

ALE/EDACK0

MTIOC4B/TMCI1

CTS2#/RTS2#/SS2#/

CTX1/ET0_LINKSTA

P53

BCLK

P51

WR1#/BC1#/

WAIT#

SCK2

VCC

TRDATA0

P80

EDREQ0

MTIOC3B/PO26

SCK10/RTS10#/

ET0_TX_EN/

RMII0_TXD_EN

MMC_D2-A/

SDHI_WP-A/

QIO2-A

K10

P76

CS6#

PO22

RXD11/ET0_RX_CLK/

REF50CK0

MMC_CMD-A/

SDHI_CMD-A/

QSSL-A

K11

PB7

A15

MTIOC3B/TIOCB5/

PO31

TXD9/ET0_CRS/

RMII0_CRS_DV

K12

PB6

A14

MTIOC3D/TIOCA5/

PO30

RXD9/ET0_ETXD1/

RMII0_TXD1

K13

PB5

A13

MTIOC2A/MTIOC1B/

TIOCB4/TMRI1/PO29/

POE4#

SCK9/RTS9#/

ET0_ETXD0/

RMII0_TXD0

P25

CS5#/

EDACK1

MTIOC4C/MTCLKB/

TIOCA4/PO5

RXD3/SMISO3/

SSCL3/SSIDATA1

HSYNC

ADTRG0#

P23

EDACK0

MTIOC3D/MTCLKD/

GTIOC0A-B/TIOCD3/

PO3

TXD3/CTS0#/RTS0#/

SMOSI3/SS0#/

SSDA3/SSISCK0

PIXD7

P16

MTIOC3C/MTIOC3D/

TIOCB1/TCLKC/

TMO2/PO14/

RTCOUT

TXD1/RXD3/SMOSI1/

SMISO3/SSDA1/

SSCL3/SCL2-DS/

USB0_VBUS/

USB0_VBUSEN/

USB0_OVRCURB

IRQ6

ADTRG0#

P24

CS4#/

EDREQ1

MTIOC4A/MTCLKA/

TIOCB4/TMRI1/PO4

SCK3/

USB0_VBUSEN/

SSISCK1

PIXCLK

P13

MTIOC0B/TIOCA5/

TMO3/PO13

TXD2/SMOSI2/

SSDA2/SDA0[FM+]

IRQ3

ADTRG1#

P56

EDACK1

MTIOC3C/TIOCA1

P52

RD#

RXD2/SMISO2/SSCL2

TRCLK

P83

EDACK1

MTIOC4C/

GTIOC0A-D

CTS10#/ET0_CRS/

RMII0_CRS_DV/

SCK10

PC5

A21/CS2#/

WAIT#

MTIOC3B/MTCLKD/

GTIOC1A-D/TMRI2/

PO29

SCK8/RSPCKA-A/

RTS8#/ET0_ETXD2

MMC_D5-A

L10

PC4

A20/CS3#

MTIOC3D/MTCLKC/

GTETRG-D/TMCI1/

PO25/POE0#

SCK5/CTS8#/

SSLA0-A/

ET0_TX_CLK

MMC_D1-A/

SDHI_D1-A/

QIO1-A/QMI-A

L11

PC2

A18

MTIOC4B/

GTIOC2B-D/TCLKA/

PO21

RXD5/SMISO5/

SSCL5/SSLA3-A/

ET0_RX_DV

MMC_CD-A/

SDHI_D3-A

L12

P73

CS3#

PO16

ET0_WOL

L13

VSS

P22

EDREQ0

MTIOC3B/MTCLKC/

GTIOC1A-B/TIOCC3/

TMO0/PO2

SCK0/

USB0_OVRCURB/

AUDIO_MCLK

PIXD6

P17

MTIOC3A/MTIOC3B/

MTIOC4B/

GTIOC0B-B/TIOCB0/

TCLKD/TMO1/PO15/

POE8#

SCK1/TXD3/SMOSI3/

SSDA3/SDA2-DS/

SSITXD0

PIXD3

IRQ7

ADTRG1#

P86

MTIOC4D/

GTIOC2B-B/TIOCA0

RXD10

PIXD1

Table 1.7

List of Pin and Pin Functions (145-Pin TFLGA) (4/5)

Number

Power Supply

Clock System

Control

I/O Port

Bus

EXDMAC

SDRAMC

Timer

Communication

Memory Interface

Camera Interface

Interrupt

S12ADC,

R12DA

145-Pin

TFLGA

(MTU, GPTA, TPU,

TMR, PPG, RTC,

CMTW, POE, CAC)

(ETHERC, SCIg,

SCIh, RSPI, RIIC,

CAN, USB, SSI)

(QSPI, SDHI,

MMCIF, PDC)

R5F564MLGDLC Scheda tecnica(PDF) 50 Page - Renesas Technology Corp

R5F564MLGDLC Scheda tecnica(HTML) 50 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Scheda tecnica Scarica

Link URL