DS1821

8 of 16

Example: CPU sets up DS1821 for low temp limit of +10

°C and high temp limit of +40°C, output active

high (i.e., DQ pin is off), then instructs the DS1821 to become a thermostat.

DQ PORT PIN

DATA (LSB

FIRST)

COMMENTS

TX

Reset

Reset pulse (480-960 µs).

RX

Presence

Presence pulse.

TX

01h

CPU issues Write TH command.

TX

28h

CPU sends data for TH limit of +40°C.

TX

Reset

Reset pulse (480-960 µs).

RX

Presence

Presence pulse.

TX

02h

CPU issues Write TL command.

TX

0Ah

CPU sends data for TL limit of +10°C.

TX

Reset

Reset pulse (480-960 µs).

RX

Presence

Presence pulse.

TX

A1h

CPU issues Read TH command.

RX

28h

DS1821 sends back stored value of TH for CPU to verify.

TX

Reset

Reset pulse (480-960 µs).

RX

Presence

Presence pulse.

TX

A2h

CPU issues Read TL command.

RX

0Ah

DS1821 sends back stored value of TL for CPU to verify.

TX

Reset

Reset pulse (480-960 µs).

RX

Presence

Presence pulse.

TX

0Ch

CPU issues Write Config command.

TX

06h

device to become thermostat.

<high impedance>

Power cycles; DS1821 now comes up in thermostat mode.

1-WIRE BUS SYSTEM

The DS1821 1-Wire bus is a system which has a single bus master and one slave. The DS1821 behaves as

a slave. The DS1821 is not able to be multidropped, unlike other 1-Wire devices from Dallas

Semiconductor.

The discussion of this bus system is broken down into three topics: hardware configuration, transaction

sequence, and 1-Wire signaling (signal types and timing).

HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to

drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open

drain or 3-state outputs. The 1-Wire port of the DS1821 (DQ pin) is open drain with an internal circuit

equivalent to that shown in Figure 4. The 1-Wire bus requires a pullup resistor of approximately 5K.