DS1821

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HARDWARE CONFIGURATION Figure 4

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus

MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between

bits so long as the 1-Wire bus is in the inactive (high) state during the recovery period. If this does not

occur and the bus is left low for more than 480

µs, all components on the bus will be reset.

TRANSACTION SEQUENCE

The protocol for accessing the DS1821 via the 1-Wire port is as follows:

• Initialization

• Function Command

• Transaction/Data

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence

consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the

slave(s).

The presence pulse lets the bus master know that the DS1821 is on the bus and is ready to operate. For

more details, see the “1-Wire Signaling” section.

1-WIRE SIGNALING

The DS1821 requires strict protocols to insure data integrity. The protocol consists of several types of

signaling on one line: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of these signals,

with the exception of the presence pulse, are initiated by the bus master.

The initialization sequence required to begin any communication with the DS1821 is shown in Figure 5.

A reset pulse followed by a presence pulse indicates the DS1821 is ready to send or receive data given the

correct function command.

The bus master transmits (TX) a reset pulse (a low signal for a minimum of 480

µs). The bus master then

releases the line and goes into a receive mode (RX). The 1-Wire bus is pulled to a high state via the 5K

pullup resistor. After detecting the rising edge on the DQ pin, the DS1821 waits 15-60

µs and then

transmits the presence pulse (a low signal for 60-240

µs).