DS2152 datasheet(13/94 Pages) DALLAS

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DS2152

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Write Input [ WR ] (Read/Write [R/ W ]). WR is an active low signal.

LINE INTERFACE PINS

Master Clock Input [MCLK]. A 1.544 MHz (± 50 ppm) clock source with TTL levels is applied at this

pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal

of 1.544 MHz may be applied across MCLK and XTALD instead of the TTL level clock source.

Quartz Crystal Driver [XTALD]. A quartz crystal of 1.544 MHz may be applied across MCLK and

XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a TTL clock source is

applied at MCLK.

Eight Times Clock [8XCLK]. A 12.352 MHz clock that is frequency locked to the 1.544 MHz clock

provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from

the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally disabled via the

TEST2 register if not needed.

Line Interface Connect [LIUC]. Tie low to separate the line interface circuitry from the

framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high

to connect the line interface circuitry to the framer/formatter circuitry and deactivate the

TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI

pins.

When

LIUC

tied

high,

the

TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be tied low.

Receive Tip and Ring [RTIP & RRING]. Analog inputs for clock recovery circuitry. These pins

connect via a 1:1 transformer to the T1 line. See Section 14 for details.

Transmit Tip and Ring [TTIP & TRING]. Analog line driver outputs. These pins connect via a 1:1.15

or 1:1.36 step-up transformer to the T1 line. See Section 14 for details.

Receive Analog Positive Supply [RVDD]. 5.0 volts ± 5%. Should be tied to the DVDD and TVDD pins.

Transmit Analog Positive Supply [TVDD]. 5.0 volts ± 5%. Should be tied to the RVDD and DVDD

pins.

Digital Signal Ground [DVSS]. Should be tied to the RVSS and TVSS pins.

Receive Analog Signal Ground [RVSS]. 0.0 volts. Should be tied to the DVSS and TVSS pins.

Transmit Analog Ground [TVSS]. 0.0 volts. Should be tied to the RVSS and DVSS pins.

SUPPLY PINS

Digital Positive Supply [DVDD]. 5.0 volts ± 5%. Should be tied to the RVDD and TVDD pins.

DS2152 REGISTER MAP Table 1-3

ADDRESS

R/W

FDL Control

FDLC

R/W

FDL Status

FDLS

R/W

FDL Interrupt Mask

FIMR

R/W

Receive Performance Report Message

RPRM

R/W

Receive Bit Oriented Code

RBOC

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