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EPF8282AV Scheda tecnica(PDF) 36 Page - Altera Corporation |
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EPF8282AV Scheda tecnica(HTML) 36 Page - Altera Corporation |
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36 / 62 page ![]() 36 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Tables 22 through 49 show the FLEX 8000 internal and external timing parameters. Table 21. FLEX 8000 Timing Model Interconnect Paths Source Destination Total Delay LE-Out LE in same LAB t LOCAL LE-Out LE in same row, different LAB t ROW + tLOCAL LE-Out LE in different row t COL + tROW + tLOCAL LE-Out IOE on column t COL LE-Out IOE on row t ROW IOE on row LE in same row t ROW + tLOCAL IOE on column Any LE t COL + tROW + tLOCAL Table 22. EPF8282A Internal I/O Element Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max tIOD 0.7 0.8 0.9 ns tIOC 1.7 1.8 1.9 ns tIOE 1.7 1.8 1.9 ns tIOCO 1.0 1.0 1.0 ns tIOCOMB 0.3 0.2 0.1 ns tIOSU 1.4 1.6 1.8 ns tIOH 0.0 0.0 0.0 ns tIOCLR 1.2 1.2 1.2 ns tIN 1.5 1.6 1.7 ns tOD1 1.1 1.4 1.7 ns tOD2 –– – ns tOD3 4.6 4.9 5.2 ns tXZ 1.4 1.6 1.8 ns tZX1 1.4 1.6 1.8 ns tZX2 –– – ns tZX3 4.9 5.1 5.3 ns |
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