AS5050A datasheet(16/31 Pages) AMSCO

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[v2-03] 2014-Jul-31

AS5050A − SPI Inter face

SPI Write Data Frame

Figure 18:

SPI Write Data Frame

The parity bit PAR is calculated for the upper 15 bits.

In a SPI write transaction, the write command frame (e.g. Write

ADD[n]) is followed by a data frame (e.g. DATA [x]). In addition

to writing an address in the AS5050A, a write command frame

causes the old contents of the addressed register (e.g. DATA [y])

to be sent on MISO in the following frame. This is followed by

the new contents of the addressed register (DATA [x]) as shown

in Figure 19.

Figure 19:

SPI Write Transaction

Bit

7654

Data 15:2

PAR

Bit

Name

Description

15:2

Data

14 bit write data

Don’t Care

PAR

Parity bit (even) calculated on the upper 15 bits

Write ADD[n]

DATA(x)

CSn

Write ADD[m]

Data ADD[n]

Data ADD[m]

DATA(x)

Command

Data to write into ADD[n]

Data content ADD[n]

Data content ADD[m]

New Data content

of ADD[n]

MOSI

MISO

DATA(y)

Data to write into ADD[m]

command

Command

DATA(y)

New Data content

of ADD[m]

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