HT47C20L datasheet(21/55 Pages) HOLTEK

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HT47C20L

January 18, 2000

Timer/event counter

One 16-bit timer/event counter with PFD out-

put or two channels of RC type A/D converter is

implemented in the HT47C20L. The ADC/TM

bit (bit 1 of ADCR register) decides whether

timer A and timer B are composed of one 16-bit

timer/event counter or timer A and timer B are

composed of two channels RC type A/D con-

verter.

The TMRAL, TMRAH, TMRBL, TMRBH com-

posed of one 16-bit timer/event counter, when

ADC/TM bit is ²0². The TMRBL and TMRBH

are timer/event counter preload registers for

lower-order byte and higher-order byte respec-

tively.

The timer/event counter clock source may come

from system clock or T1 (system clock/4) or real

time clock time-out signal or external source.

The external clock input allows the user to count

external events, count external RC type A/D clock,

measure time intervals or pulse widths, or gener-

ate an accurate time base.

There are six registers related to the timer/event

counter operating mode. TMRAH ([20H]), TMRAL

([21H]), TMRC ([22H]), TMRBH ([23H]), TMRBL

([24H]) and ADCR ([25H]). Writing to TMRBL

only writes the data into a low byte buffer, and

writing to TMRBH will write the data and the

contents of the low byte buffer into the time/event

counter preload register (16-bit) simultaneously.

The timer/event counter preload register is

changed by writing to TMRBH operations and

writing to TMRBL will keep the timer/event

counter preload register unchanged.

Reading TMRAH will also latch the TMRAL

into the low byte buffer to avoid the false timing

problem. Reading TMRAL returns the contents

of the low byte buffer. In other words, the low

byte of the timer/event counter can not be read

directly. It must read the TMRAH first to make

the low byte contents of timer/event counter be

latched into the buffer.

The TMRC is the timer/event counter control

options.

The timer/event counter control register define

the operating mode, counting enable or disable

and active edge.

Writing to timer B location puts the starting

value in the timer/event counter preload regis-

ter, while reading timer A yields the contents of

the timer/event counter. Timer B is timer/event

counter preload register.

The TN0, TN1 and TN2 bits define the opera-

tion mode. The event count mode is used to

count external events, which means that the

clock source comes from an external (TMR) pin.

The A/D clock mode is used to count external

A/D clock, the RC oscillation mode is decided by

ADCR register. The timer mode functions as a

normal timer with the clock source coming from

the internal selected clock source. Finally, the

pulse width measurement mode can be used to

count the high or low level duration of the ex-

ternal signal (TMR). The counting is based on

the T1 (system clock/4).

In the event count, A/D clock or internal timer

mode, once the timer/event counter starts

counting, it will count from the current con-

Sy s t e m C l o c k

TM R 0

TN 1

TN 0

TO N

P u l s e W i dt h

M eas ur e m ent

M ode C ont r o l

16 bi t T i m er A

16 b i t T i m e r B

Da t a B u s

RE L O A D

ov er f l o w

TN 2

PF D

PA3 D a t a C T R L

R e a l ti m e c l o c k o u tpu t

A/ D C l o c k

TN 1

TN 0

TN 2

Timer/event counter

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