HT47C20L datasheet(28/55 Pages) HOLTEK

28 / 55 page

HT47C20L

January 18, 2000

Da t a B u s

WE A K

Pu l l - u p

PA0 / B Z

V DD

Ma s k

Opt i o n

V DD

B Z O pti o n

R ead P a t h

B Z S i gnal

WE A K

Pu l l - u p

PA1 / B Z

V DD

Ma s k

Opt i o n

V DD

B Z O pti o n

R ead P a t h

C h i p R es et

M a sk O pt i o n

S y s t em W ak e- up

M a sk O pt i o n

S y s t em W ak e- up

Da t a B u s

C h i p R es et

PA0/BZ, PA1/BZ input/output lines

Input/output ports

There are 8-bit bidirectional input/output port

and 4-bit input port in the HT47C20L, labeled

PA and PB which are mapped to the data mem-

ory of [12H] and [14H] respectively. The high

nibble of the PA is NMOS output and input with

pull-high resistors. The low nibble of the PA can

be used for input/output or output operation by

selecting NMOS or CMOS output by mask op-

tion. Each bit on the PA can be configured as a

wake-up input and the low nibble of the PA with

or without pull-high resistors by mask option.

PB can only be used for input operation, and

each bit on the port can be configured with pull

high resistor. Both are for the input operation,

these ports are non-latched, that is, the inputs

should be ready at the T2 rising edge of the in-

struction ²MOV A, [m]² (m=12H or 14H). For

PA output operation, all data are latched and

remain unchanged until the output latch is re-

written.

When the structures of PA are open drain NMOS

type, it should be noted that, before reading data

from the pads a ²1² should be written to the re-

lated bits to disable the NMOS device. That is

done first before executing the instruction ²MOV

A, 0FFH² and ²MOV [12H], A² to disable the re-

lated NMOS device, and then ²MOV A, [12H]² to

get a stable data.

After chip reset, these input lines remain at a

high level or are left floating (by mask option).

Some instructions first input data and then fol-

low the output operations. For example, ²SET

[m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read

the entire port states into the CPU, execute the

defined operations (bit-operation), and then write

the results back to the latches or to the accumula-

tor. Each bit of the PA output latches can not use

these instruction, which may change the input

lines to output lines (when the input lines are at

low level).

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